Automating the production of a fully routed and design rule compliant design involves a high level of computational complexity. Therefore, a given router might not be able to achieve 100% routing completion in a single run. Design rule constraints at the transistor level are quite rigorous, necessitating intelligent strategies to resolve incomplete routes. For example, design rule constraints (e.g., spacing requirements) for the contact layers between the transistor terminals and the metal 1 (M1) layer are complex and difficult to satisfy, especially as semiconductor fabrication technologies approach 10 nm and below. Applying simple strategies for resolving incomplete routes (e.g., route extensions or relocating existing routes to make room for other routes) may result in a combinatorial explosion of the search space.